Design a specific counts counter (counting sequence listed below) using ROM to develop a Mealy state machine.
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Design a specific counts counter (counting sequence listed below) using ROM to develop a Mealy state machine. Develop a testbench and verify the model through behavioral simulation. Use SW15 as the clock input, the BTNU button as reset input to the circuit, and LED2:LED0 as the count output of the counter. Go through the design flow, generate the bitstream, and download it into the Basys3 or the Nexys4 DDR board. Verify the functionality. The counting sequence will be: 0000, 0001, 0110, 1001, 1111, 0100 (repeat) 0000, ...
Related Book For
Digital Systems Design Using Verilog
ISBN: 978-1285051079
1st edition
Authors: Charles Roth, Lizy K. John, Byeong Kil Lee
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