draw the pipeline execution diagram for the following RISC-V instructions. We assume that the code is...

 

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draw the pipeline execution diagram for the following RISC-V instructions. We assume that the code is executed on a pipelined processor with a 5-stage pipeline, full forwarding, and a predict-taken branch predictor. In addition, assuming that branches execute in the EX stage. (4 marks) Iw x11, 0(x10) label1: beq x11, x0, label2 # not taken once, then taken Iw x12, 0(x11) beq x12, x0, label1 # taken add x10, x12, x11 label2: sw x10, 0(x11) Activate Windows Go to Settings to activate draw the pipeline execution diagram for the following RISC-V instructions. We assume that the code is executed on a pipelined processor with a 5-stage pipeline, full forwarding, and a predict-taken branch predictor. In addition, assuming that branches execute in the EX stage. (4 marks) Iw x11, 0(x10) label1: beq x11, x0, label2 # not taken once, then taken Iw x12, 0(x11) beq x12, x0, label1 # taken add x10, x12, x11 label2: sw x10, 0(x11) Activate Windows Go to Settings to activate