Examine the difficulty of adding a proposed ss rsl, rs2, imm (Store Sum) instruction to RISC-V....

 

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Examine the difficulty of adding a proposed ss rsl, rs2, imm (Store Sum) instruction to RISC-V. Interpretation: Mem[Reg[rsl]] = Reg[rs2]+immediate. a) Which new functional blocks (if any) do we need for this instruction? %3D b) Which existing functional blocks (if any) require modification? c) What new signals do we need (if any) from the control unit to support this instruction? d) Modify the figure below to demonstrate an implementation of this new instruction. Add Add Sum Shift left 1 Branch MemRead MemtoReg ALUOP MemWrite ALUSre RegWrite Instruction (6-0] Control Instruction (19-15) Read Read address PC register 1 Instruction [24-20] Read data 1 Read register 2 Zero ALU ALU Instruction (31-0) Instruction (11-7] Read Read data Write Address Instruction memory result register data 2 Write data Registers Data Write data memory Instruction (31-0 32 64 Imm Gen ALU control Instruction (30, 14-12] Examine the difficulty of adding a proposed ss rsl, rs2, imm (Store Sum) instruction to RISC-V. Interpretation: Mem[Reg[rsl]] = Reg[rs2]+immediate. a) Which new functional blocks (if any) do we need for this instruction? %3D b) Which existing functional blocks (if any) require modification? c) What new signals do we need (if any) from the control unit to support this instruction? d) Modify the figure below to demonstrate an implementation of this new instruction. Add Add Sum Shift left 1 Branch MemRead MemtoReg ALUOP MemWrite ALUSre RegWrite Instruction (6-0] Control Instruction (19-15) Read Read address PC register 1 Instruction [24-20] Read data 1 Read register 2 Zero ALU ALU Instruction (31-0) Instruction (11-7] Read Read data Write Address Instruction memory result register data 2 Write data Registers Data Write data memory Instruction (31-0 32 64 Imm Gen ALU control Instruction (30, 14-12]

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a No new functional blocks are required to implement t... View the full answer