Fill in the ans 0-9 in the verilog code below for the FSM 1 // Design...

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Fill in the ans 0-9 in the verilog code below for the FSM 1 // Design 2 module FSM (clk, reset, X, Y); input clk, reset, X; output Y; localparam A = 2'b00, B = 2'b01, (= 2 b10, D = 2'b11; reg [1:0] curr_state, next_state; always@ (posedge clk) begin if (reset) curr_state CAS case A: begin if (X) next state = [ans3]; else next_state = [ans4]; end B: begin next_state= [ans5]; end C: begin if (X) next_state = [ans6]; else next_state = [ans7]; end D: begin if (X) next_state = [ans8]; else next_state = [ans9]; end endcase end endmodule e and Submit to , ans1 = ans3 = , ans5 = 1 , ans7 = ans9 = Fill in the ans 0-9 in the verilog code below for the FSM 1 // Design 2 module FSM (clk, reset, X, Y); input clk, reset, X; output Y; localparam A = 2'b00, B = 2'b01, (= 2 b10, D = 2'b11; reg [1:0] curr_state, next_state; always@ (posedge clk) begin if (reset) curr_state CAS case A: begin if (X) next state = [ans3]; else next_state = [ans4]; end B: begin next_state= [ans5]; end C: begin if (X) next_state = [ans6]; else next_state = [ans7]; end D: begin if (X) next_state = [ans8]; else next_state = [ans9]; end endcase end endmodule e and Submit to , ans1 = ans3 = , ans5 = 1 , ans7 = ans9 =

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