Given the following code: module clock_gate (input wire clk, enable, din, set, output reg dout); always...

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Given the following code: module clock_gate (input wire clk, enable, din, set, output reg dout); always @ (negedge clk or posedge set) begin if (set) dout <= 1'b1; else if (enable) dout <= din; end endmodule a. Synthesize to insert clock gating circuitry. 15pts b. Instantiate the original code and netlist in a testbench and test them in parallel to verify identical functionality. Compare the output of both models and increment an error counter if they differ. Turn in your testbench code, the netlist, and a waveform showing the I/O of the original code, I/O of the netlist, and an error counter. (20pts) Given the following code: module clock_gate (input wire clk, enable, din, set, output reg dout); always @ (negedge clk or posedge set) begin if (set) dout <= 1'b1; else if (enable) dout <= din; end endmodule a. Synthesize to insert clock gating circuitry. 15pts b. Instantiate the original code and netlist in a testbench and test them in parallel to verify identical functionality. Compare the output of both models and increment an error counter if they differ. Turn in your testbench code, the netlist, and a waveform showing the I/O of the original code, I/O of the netlist, and an error counter. (20pts)

Answer rating: 100% (QA)

a Synthesize to insert clock gating circuitry Assuming the clock gate module is implemented using a D flipflop the following RTL code can be used to i... View the full answer