solve the following Computer Architecture and Organisation Problem on (Instruction Set Architecture and designing of processor)? Please
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solve the following Computer Architecture and Organisation Problem on (Instruction Set Architecture and designing of processor)? Please show me the step by step solution on how to design. Thank you.
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7. Given the ISA of Processor pico CP-SYS 2013 and components, • General Purpose Register of 4 x 8 bits. . Memory with 8-bit address and 8-bit data bus • • Extender will give {0000,[immediate]} and {[immediate],0000} depending on EXT_OP (0 and 1 respectively) Instruction Memory and Data Memory are sperated. You may use unlimited numbers of multiplexor, adder and register 7 Instructions LI $immediate (I-Type), opcode = 1100 PC-PC+1, REG[3]={0000,[immediate]} LUI $Immediate (I-Type), opcode = 1101 PC-PC+1, REG[3]={[immediate],0000} • ALU with the following operation (Z=1 when S is 0.) LW $RD, $RS (R-Type), opcode = 1000 ALU_OP DESCRIPTION PC=PC+1, REG[RD]=MEM[REG[RS]] 00 01 10 11 S=A+B S=A S=B S=0 SW $RD, $RS (R-Type), opcode = 1001 PC=PC+1, MEM[REG[RS]]=REG[RD] ADD $RD, $RS (R-Type), opcode = 0010 2 instruction formats (8 bit) Format (#bit) PC-PC+1, REG[RD]=REG[RD]+REG[RS] MOV $RD, $RS (R-Type), opcode = 0011 PC-PC+1, REG[RD]=REG[RS] R-type OP RD RS BZ $RD, $RS (R-Type), opcode = 0111 I-Type OP Immediate IF (REG[RS]==0) PC=PC+REG[RD]+1 ELSE PC=PC+1 Please design the complete Data Path of Processor pico CP-SYS 2013 7. Given the ISA of Processor pico CP-SYS 2013 and components, • General Purpose Register of 4 x 8 bits. . Memory with 8-bit address and 8-bit data bus • • Extender will give {0000,[immediate]} and {[immediate],0000} depending on EXT_OP (0 and 1 respectively) Instruction Memory and Data Memory are sperated. You may use unlimited numbers of multiplexor, adder and register 7 Instructions LI $immediate (I-Type), opcode = 1100 PC-PC+1, REG[3]={0000,[immediate]} LUI $Immediate (I-Type), opcode = 1101 PC-PC+1, REG[3]={[immediate],0000} • ALU with the following operation (Z=1 when S is 0.) LW $RD, $RS (R-Type), opcode = 1000 ALU_OP DESCRIPTION PC=PC+1, REG[RD]=MEM[REG[RS]] 00 01 10 11 S=A+B S=A S=B S=0 SW $RD, $RS (R-Type), opcode = 1001 PC=PC+1, MEM[REG[RS]]=REG[RD] ADD $RD, $RS (R-Type), opcode = 0010 2 instruction formats (8 bit) Format (#bit) PC-PC+1, REG[RD]=REG[RD]+REG[RS] MOV $RD, $RS (R-Type), opcode = 0011 PC-PC+1, REG[RD]=REG[RS] R-type OP RD RS BZ $RD, $RS (R-Type), opcode = 0111 I-Type OP Immediate IF (REG[RS]==0) PC=PC+REG[RD]+1 ELSE PC=PC+1 Please design the complete Data Path of Processor pico CP-SYS 2013
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We must incorporate parts for instruction fetch decode execute and memory access in order to construct the entire data path for the specified CPU Lets ... View the full answer
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