i need help with my quartas verilog code : ENTITY Tb_Carry_Look_Ahead IS END ENTITY Tb_Carry_Look_Ahead; ARCHITECTURE behavior
Question:
i need help with my quartas verilog code :
ENTITY Tb_Carry_Look_Ahead IS
END ENTITY Tb_Carry_Look_Ahead;
ARCHITECTURE behavior OF Tb_Carry_Look_Ahead IS
COMPONENT Carry_Look_Ahead
PORT (
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
Cin : IN std_logic;
S : OUT std_logic_vector(3 downto 0);
Cout : OUT std_logic
);
END COMPONENT;
signal A : std_logic_vector(3 downto 0) := (others => '0');
signal B : std_logic_vector(3 downto 0) := (others => '0');
signal Cin : std_logic := '0';
signal S : std_logic_vector(3 downto 0);
signal Cout : std_logic;
BEGIN
uut: Carry_Look_Ahead PORT MAP (
A => A,
B => B,
Cin => Cin,
S => S,
Cout => Cout
);
stim_proc: process
begin
-- Hold reset state for 100 ns.
wait for 100 ns;
A B Cin wait for 100 ns;
A B Cin wait for 100 ns;
A B Cin wait;
end process;
END ARCHITECTURE behavior;
Income Tax Fundamentals 2013
ISBN: 9781285586618
31st Edition
Authors: Gerald E. Whittenburg, Martha Altus Buller, Steven L Gill