I o The diagram below is adapted from Figure 2.16 as printed on p.49 of our...
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I o The diagram below is adapted from Figure 2.16 as printed on p.49 of our reference book #1 ("Microprocessors and Microcomputers"). Assume the serial input I = 0, with [X] = 1012 and [Y] = 1102 initially. (12%)< X register SHIFT pulses S R X₂ X₂ CLK S X₁ 20 IX CLK S X X R Xo CLK S R الانه Y₂ CLK Y register S 20 CLK XI S R CLK Yo i. Determine the final content of the register X at the end of 2 SHIFT pulses.< ii. Also determine the final content of the register Y at the end of 3 SHIFT pulses.< iii. Modify the above circuit so that at the end of the third SHIFT pulse, the = contents of both registers X and Y are swapped, i.e. [X] = 1102 and [Y] = 1012.< (b) Compare the relative advantages of parallel and serial transfer of data between two registers. (8%)< K I o The diagram below is adapted from Figure 2.16 as printed on p.49 of our reference book #1 ("Microprocessors and Microcomputers"). Assume the serial input I = 0, with [X] = 1012 and [Y] = 1102 initially. (12%)< X register SHIFT pulses S R X₂ X₂ CLK S X₁ 20 IX CLK S X X R Xo CLK S R الانه Y₂ CLK Y register S 20 CLK XI S R CLK Yo i. Determine the final content of the register X at the end of 2 SHIFT pulses.< ii. Also determine the final content of the register Y at the end of 3 SHIFT pulses.< iii. Modify the above circuit so that at the end of the third SHIFT pulse, the = contents of both registers X and Y are swapped, i.e. [X] = 1102 and [Y] = 1012.< (b) Compare the relative advantages of parallel and serial transfer of data between two registers. (8%)< K
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Related Book For
Fundamentals Of Digital Logic With Verilog Design
ISBN: 9780073380544
3rd Edition
Authors: Stephen Brown, Zvonko Vranesic
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