Influence of the number of processors on miss rate in multiprocessor Purpose: Study the influence of the number of processors on the miss rate during the execution of a parallel program in a symmetric multiprocessor. Development: Configure a system with the following architectural characteristics: - Cache coherence protocol = MESI. - Scheme for bus arbitration = LRU. - Word wide (bits) =16. - Words by block =32 (block size =64 bytes). - Blocks in main memory =524288 (main memory size =32 MB ), - Clocks in cache =256 (cache size =16 KB ). - Mapping = Set-Associative. - Cache sets =64 (four-way set associative caches). - Replacement policy - LRU. Configure the number of processors in the SMP using the following configurations: 1,2 , 4 , and 8. For each of the configurations, obtain the global miss rate for the system using the F F T traces that were given. Discussions: Does the global miss rate increase or decrease as the number of processors increases? Why? Does this increment or decrement happen for all the benchmarks or does it depend on the different locality grades, shared data,...? What does it happen with the capacity and coherence misses when you enlarge the number of processors? Are there conflict misses in these experiments? Why? Do you think that the results and conclusions obtained with these experiments are of general application or they may change depending on the cache coherence protocol? Why? In conclusion, does the increase of the number of processors improve the multiprocessor system performance? Why and in what sense?

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