Loop: LD DADDI SD DADDI DSUB BNEZ Use the following code fragment: R1,0 (R2) R1, R1,...

  

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Loop: LD DADDI SD DADDI DSUB BNEZ Use the following code fragment: R1,0 (R2) R1, R1, #1 R1,0, (R2) ;load R1 from address 0+R2 ;RI=R1+1 store R1 at address 0+R2 R2-R2+4 ;R4-R3-R2 ;branch to Loop if R4!=0 R2, R2,#4 R4, R3, R2 R4, Loop Assume that the initial value of R3 is R2 +396. a. [15] Data hazards are caused by data dependences in the code. Whether a dependency causes a hazard depends on the machine implementa- tion (i.e., number of pipeline stages). List all of the data dependences in the code above. Record the register, source instruction, and destination instruc- tion; for example, there is a data dependency for register RI from the LD to the DADDI. b. [15] Show the timing of this instruction sequence for the 5-stage RISC pipeline without any forwarding or bypassing hardware but assuming that a register read and a write in the same clock cycle "forwards" through the reg- ister file, as shown in Figure C.6. Use a pipeline timing chart like that in Fig- ure C.5. Assume that the branch is handled by flushing the pipeline. If all memory references take 1 cycle, how many cycles does this loop take to exe- cute? c. [15] Show the timing of this instruction sequence for the 5-stage RISC pipeline with full forwarding and bypassing hardware. Use a pipeline timing chart like that shown in Figure C.5. Assume that the branch is handled predicting it as not taken. If all memory references take 1 cycle, how many cycles does this loop take to execute? Loop: LD DADDI SD DADDI DSUB BNEZ Use the following code fragment: R1,0 (R2) R1, R1, #1 R1,0, (R2) ;load R1 from address 0+R2 ;RI=R1+1 store R1 at address 0+R2 R2-R2+4 ;R4-R3-R2 ;branch to Loop if R4!=0 R2, R2,#4 R4, R3, R2 R4, Loop Assume that the initial value of R3 is R2 +396. a. [15] Data hazards are caused by data dependences in the code. Whether a dependency causes a hazard depends on the machine implementa- tion (i.e., number of pipeline stages). List all of the data dependences in the code above. Record the register, source instruction, and destination instruc- tion; for example, there is a data dependency for register RI from the LD to the DADDI. b. [15] Show the timing of this instruction sequence for the 5-stage RISC pipeline without any forwarding or bypassing hardware but assuming that a register read and a write in the same clock cycle "forwards" through the reg- ister file, as shown in Figure C.6. Use a pipeline timing chart like that in Fig- ure C.5. Assume that the branch is handled by flushing the pipeline. If all memory references take 1 cycle, how many cycles does this loop take to exe- cute? c. [15] Show the timing of this instruction sequence for the 5-stage RISC pipeline with full forwarding and bypassing hardware. Use a pipeline timing chart like that shown in Figure C.5. Assume that the branch is handled predicting it as not taken. If all memory references take 1 cycle, how many cycles does this loop take to execute?

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The image contains a code fragment and questions about data hazards and pipeline timing related to the execution of the code on a 5stage RISC Reduced Instruction Set Computer processor The code fragme... View the full answer