Mark all of the following that are valid design reasons that the FP and integer registers...

 

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Mark all of the following that are valid design reasons that the FP and integer registers in the MIPS DLX ISA are logically separated U 0 Floating point registers need their bits stored on floating gates Integer operands are big endian and floating point operands are little endian The original MIPS ISA used a co-processor model for communicating with the floating-point unit Integer instructions rarely use floating point operands, and vice versa Mark all of the following that are valid design reasons that the FP and integer registers in the MIPS DLX ISA are logically separated U 0 Floating point registers need their bits stored on floating gates Integer operands are big endian and floating point operands are little endian The original MIPS ISA used a co-processor model for communicating with the floating-point unit Integer instructions rarely use floating point operands, and vice versa