cess parameters: Consider a pMOS transistor with the following pro- tor = 9.6 nm Hp 232cm/V-sec...

   

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cess parameters: Consider a pMOS transistor with the following pro- tor = 9.6 nm Hp 232cm²/V-sec - Esat 4 x 10'V/cm VT=-1V The device is operating at T = 300 K (kT/q = 26mV). The following equations are valid for velocity-saturated devices: W Cor (VSG-VT) VSD - 0.5VD] ISD,triode (1) L 1+ VSD/(Esat L) 2(VSG-|VT) VSD.sat (2) 1+2(VSGVT)/(Esat L) +1 = (a) Consider one of these pMOS transistors with Ldrawn = 0.6μm and Wdrawn 10μm. Assume that the effective and drawn dimensions are identical (AW = 0 and AL=0). Considering velocity saturation (using the equations above), plot Ip as a function of Vsp between 0 and 5.0 V for Vsc = 0, 0.5, 1.0, 1.5, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0 V. Assume VSB = 0. What effect (qualitatively) does velocity saturation have on the current drive of the FET compared to a case in which the carrier drift velocity does not saturate? (b) Assume that STI (shallow trench isolation) is used so that sidewall capacitance can be largely ignored for the source-drain diffusions. Assume that the source- substrate and drain-substrate areal capacitances are defined by an abrupt junction between a source-drain doping of NA = 1 x 1018 cm³ and a substrate doping of ND = 8 × 1016 cm 3. Consider two pMOS transistors in series as shown in the schematic below. The capacitance of node C is dominated by the diffusion capacitance of the source-drain region. If the diffusion area of node C is 30 μm², what are the largest and smallest possible values of this diffusion capacitance (over the possible reverse biases on this node with respect to the nwell)? A B C +5V cess parameters: Consider a pMOS transistor with the following pro- tor = 9.6 nm Hp 232cm²/V-sec - Esat 4 x 10'V/cm VT=-1V The device is operating at T = 300 K (kT/q = 26mV). The following equations are valid for velocity-saturated devices: W Cor (VSG-VT) VSD - 0.5VD] ISD,triode (1) L 1+ VSD/(Esat L) 2(VSG-|VT) VSD.sat (2) 1+2(VSGVT)/(Esat L) +1 = (a) Consider one of these pMOS transistors with Ldrawn = 0.6μm and Wdrawn 10μm. Assume that the effective and drawn dimensions are identical (AW = 0 and AL=0). Considering velocity saturation (using the equations above), plot Ip as a function of Vsp between 0 and 5.0 V for Vsc = 0, 0.5, 1.0, 1.5, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0 V. Assume VSB = 0. What effect (qualitatively) does velocity saturation have on the current drive of the FET compared to a case in which the carrier drift velocity does not saturate? (b) Assume that STI (shallow trench isolation) is used so that sidewall capacitance can be largely ignored for the source-drain diffusions. Assume that the source- substrate and drain-substrate areal capacitances are defined by an abrupt junction between a source-drain doping of NA = 1 x 1018 cm³ and a substrate doping of ND = 8 × 1016 cm 3. Consider two pMOS transistors in series as shown in the schematic below. The capacitance of node C is dominated by the diffusion capacitance of the source-drain region. If the diffusion area of node C is 30 μm², what are the largest and smallest possible values of this diffusion capacitance (over the possible reverse biases on this node with respect to the nwell)? A B C +5V