The IE and IP registers of Intel 8051 and the interrupt vector address table are given...

 

Transcribed Image Text:

The IE and IP registers of Intel 8051 and the interrupt vector address table are given at the end. Configure the IE and IP registers to enable Timer 1 and External Interrupt 1, but Timer 1 with a higher interrupt priority than External Interrupt 1. A. Draw the registers and show your values in hex, next to each register. B. How is Timer 1 overflow detected and where will the execution jump when the interrupt is serviced? C. While External Interrupt 1 subroutine is running Timer 1 overflows, causing a nested interrupt. What will happen? BIT IP.7 IP.6 IP.5 IP4 IP.3 IP2 IP.1 IP.0 Source IEO #3333359 TFO IE1 TF1 RI+TI BIT E.7 E.B E.5 ICA E3 E2 E.1 - PS PTI SYMBOL FUNCTION Reservad PX1 PTO PKD INTERRUPT PRIORITY & INTERRUPT VECTOR ADDRESS TABLE Vector Address 0003H 000BH MSB 1186568 X ETI EXT ETO EXO X MSB Reserved. Reserved. 0013H 001BH 0023H EA SYMBOL FUNCTION EA 8051 REFERRENCE MANUAL X X Defines the Serial Port interrupt priority level. PS-1 programs it to the higher priority level Delines the Timer 1 interrupt priority level. PT1-1 programs t to the higher priority level. Defines the External Interupt 1 priority laval. PX1=1 programs it to the higher priority level Enables or disables the Timer O interrupt priority level. FTO-1 programs it to the higher onorty level Delfines the ExternalInterrupt 0 priority level. PXD-1 programs it to the higher priority level. PS LSE PT1 FX1 PTO PXO Figure 19. Interrupt Prionty Register (F) X Contains JMP OB00 RETI JMP 0B80 RETI JMP 0C00 RETI JMP 0C80 RETI JMP 0D00 RETI ES LSB ETI EX1 ETD EXD Disables all interrupts. Ir EA-0, no interupt will be acknowledged If EA-1, each interrupt source is individually enabled or disabled by seting or clearing its enable bit Reserved Reserved Chables or disables the Serial Port interupt FC0-0, the Serial Port intempt is disabled Enables or disables the Timer 1 Overflow intenupt ET1-0, the Timer 1 interact is disabled Enables or disables External interrupt 1. I EX1-0, External interrupt 1 is disabled. Enables or disables the Timer 0 Overflow interrupt ETD-0, the Timer Ortemapt is disabled Snables or disables External interrupt 0.1 EXO-C, External interrupt is disabled Figure 18 Interruct Enable Register (E) BUCOSAS BISH The IE and IP registers of Intel 8051 and the interrupt vector address table are given at the end. Configure the IE and IP registers to enable Timer 1 and External Interrupt 1, but Timer 1 with a higher interrupt priority than External Interrupt 1. A. Draw the registers and show your values in hex, next to each register. B. How is Timer 1 overflow detected and where will the execution jump when the interrupt is serviced? C. While External Interrupt 1 subroutine is running Timer 1 overflows, causing a nested interrupt. What will happen? BIT IP.7 IP.6 IP.5 IP4 IP.3 IP2 IP.1 IP.0 Source IEO #3333359 TFO IE1 TF1 RI+TI BIT E.7 E.B E.5 ICA E3 E2 E.1 - PS PTI SYMBOL FUNCTION Reservad PX1 PTO PKD INTERRUPT PRIORITY & INTERRUPT VECTOR ADDRESS TABLE Vector Address 0003H 000BH MSB 1186568 X ETI EXT ETO EXO X MSB Reserved. Reserved. 0013H 001BH 0023H EA SYMBOL FUNCTION EA 8051 REFERRENCE MANUAL X X Defines the Serial Port interrupt priority level. PS-1 programs it to the higher priority level Delines the Timer 1 interrupt priority level. PT1-1 programs t to the higher priority level. Defines the External Interupt 1 priority laval. PX1=1 programs it to the higher priority level Enables or disables the Timer O interrupt priority level. FTO-1 programs it to the higher onorty level Delfines the ExternalInterrupt 0 priority level. PXD-1 programs it to the higher priority level. PS LSE PT1 FX1 PTO PXO Figure 19. Interrupt Prionty Register (F) X Contains JMP OB00 RETI JMP 0B80 RETI JMP 0C00 RETI JMP 0C80 RETI JMP 0D00 RETI ES LSB ETI EX1 ETD EXD Disables all interrupts. Ir EA-0, no interupt will be acknowledged If EA-1, each interrupt source is individually enabled or disabled by seting or clearing its enable bit Reserved Reserved Chables or disables the Serial Port interupt FC0-0, the Serial Port intempt is disabled Enables or disables the Timer 1 Overflow intenupt ET1-0, the Timer 1 interact is disabled Enables or disables External interrupt 1. I EX1-0, External interrupt 1 is disabled. Enables or disables the Timer 0 Overflow interrupt ETD-0, the Timer Ortemapt is disabled Snables or disables External interrupt 0.1 EXO-C, External interrupt is disabled Figure 18 Interruct Enable Register (E) BUCOSAS BISH

Answer rating: 100% (QA)

Unfortunately the question image appears to be incomplete and I cant provide a full response without the full text of the question or the complete cha... View the full answer