The instructions in the VeryFast architecture can be divided into four classes according to their CPI:...

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The instructions in the VeryFast architecture can be divided into four classes according to their CPI: class A, B, C, and D. Two processors P1 and P2 are designed based on the VeryFast architecture. P1 has a clock rate of 3.3 GHz and CPIs of 1, 2, 2, and 2, and P2 has a clock rate of 2.7 GHz and CPIs of 4, 2, 1, and 1. We are given a program X, which has a dynamic instruction count of 1.5 million. The instruction distribution is as follows: 12.5% class A, 10% class B, 70% class C, and 7.5% class D. (a) What is the effective CPI for program X on P1 and P2? (b) What is the total elapsed clock cycles when executing program X on P1 and P2? (c) Which processor implementation has a lower runtime for program X? The instructions in the VeryFast architecture can be divided into four classes according to their CPI: class A, B, C, and D. Two processors P1 and P2 are designed based on the VeryFast architecture. P1 has a clock rate of 3.3 GHz and CPIs of 1, 2, 2, and 2, and P2 has a clock rate of 2.7 GHz and CPIs of 4, 2, 1, and 1. We are given a program X, which has a dynamic instruction count of 1.5 million. The instruction distribution is as follows: 12.5% class A, 10% class B, 70% class C, and 7.5% class D. (a) What is the effective CPI for program X on P1 and P2? (b) What is the total elapsed clock cycles when executing program X on P1 and P2? (c) Which processor implementation has a lower runtime for program X?