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Write the VHDL code that implements the logic circuit with three inputs (A, B, C) and one output (F) using a 2x1 MUX (multiplexer) below,

Write the VHDL code that implements the logic circuit with three inputs (A, B, C) and one output (F) using a 2x1 MUX (multiplexer) below, as well as the test bench code.

F 2x1 MUX I S A BC

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