(a) For the circuit in Figure P16.62, make a table showing the state of each transistor ("on" or "off"), and determine the output voltages \(v_{O 1}, v_{O 2}\), and \(v_{\mathrm{O} 3}\) for the input logic states listed in the following table. Assume the input conditions are sequential in time from state 1 to state 6.

(b) What logic function does the circuit implement?

Transcribed Image Text:

State CLK Vy Vz 123456 0 1 0 1 0 O 1100 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1