Assume the circuit shown in Figure P10.54 is biased at (V^{+}=3 mathrm{~V}) and (V^{-}=-3 mathrm{~V}). The transistor

Question:

Assume the circuit shown in Figure P10.54 is biased at $V^{+}=3 \mathrm{~V}$ and $V^{-}=-3 \mathrm{~V}$. The transistor parameters are $V_{T P}=-0.5 \mathrm{~V}, k_{p}^{\prime}=60 \mu \mathrm{A} / \mathrm{V}^{2}$, and $\lambda=0$. Design the circuit such that $I_{\mathrm{REF}}=250 \mu \mathrm{A}, I_{O}=80 \mu \mathrm{A}$, and $V_{S D 2}(\mathrm{sat})=1.0 \mathrm{~V}$. Assume $M_{3}$ and $M_{4}$ are matched.

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