Consider the circuit shown in Figure P10.67. The transistor parameters are \(V_{T N}=0.4 \mathrm{~V}, k_{n}^{\prime}=100 \mu \mathrm{A} / \mathrm{V}^{2}\), and \(\lambda=0\). Design the \((W / L)\) ratios of the transistors such that the total power dissipated in the circuit is \(5 \mathrm{~mW}\) and \(V_{D S 2}(\mathrm{sat})=0.4 \mathrm{~V}\).

Transcribed Image Text:

V+ 1.8 V TREF 4 Load 1 | 101 = 0.1 mA M M2 V=-1.8 V Figure P10.67 Load 2 |102= 0.2 mA M3 Load 3 ||103= 0.4 mA MA