Consider the voltage doubler circuit in Figure 2.14. Assume a \(60 \mathrm{~Hz}\), \(120 \mathrm{~V}\) (rms) signal is applied at the input of the transformer with a \(20: 1\) turns ratio. Let \(R=10 \mathrm{k} \Omega\) and \(C_{1}=C_{2}=200 \mu \mathrm{F}\). Using a computer simulation, plot the output voltage over four cycles of input voltage.

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D + 10 ww RL D Figure 2.14 A voltage doubler circuit