The circuit in Figure 8.31 is to be designed such that the quiescent collector currents are \(4 \mathrm{~mA}\left(v_{O}=0\right)\). Assume \(I_{S Q}=2 \times 10^{-15} \mathrm{~A}\) and \(I_{S D}=\) \(4 \times 10^{-16} \mathrm{~A}\). Neglecting base currents,

(a) determine the required value of \(I_{\text {Bias }}\),

(b) the resulting value of \(V_{B B}\), and

(c) the required value of \(v_{I}\).

Transcribed Image Text:

V+ Bias iBn iCn Qn DIS VBB D2V RL Qp 'Bp icp Figure 8.31