The CMOS inverter in Figure 16.21 is biased at (V_{D D}=3.3 mathrm{~V}). Let (K_{n}=K_{p}), (V_{T N}=0.5 mathrm{~V}),

Question:

The CMOS inverter in Figure 16.21 is biased at $V_{D D}=3.3 \mathrm{~V}$. Let $K_{n}=K_{p}$, $V_{T N}=0.5 \mathrm{~V}$, and $V_{T P}=-0.5 \mathrm{~V}$.

(a) Determine the two values of $v_{I}$ and the corresponding values of $v_{O}$ for which $\left(d v_{O} / d v_{I}\right)=-1$ on the voltage transfer characteristics.

(b) Find the noise margins.

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