The diff-amp configuration shown in Figure P11.7 is biased at \(\pm 3 \mathrm{~V}\). The maximum power dissipation in the entire circuit is to be no more than \(1.2 \mathrm{~mW}\) when \(v_{1}=v_{2}=0\). The available transistors have parameters: \(\beta=120, V_{B E}\) (on) \(=0.7 \mathrm{~V}\), and \(V_{A}=\infty\). Design the circuit to produce the maximum possible differential-mode voltage gain, but such that the common-mode input voltage can be within the range \(-1 \leq v_{C M} \leq 1 \mathrm{~V}\) and the transistors are still biased in the forward-active region. What is the value of \(A_{d}\) ? What are the current and resistor values?

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V+ ic = Rc Rc 1+8m www UCI UC2 Q2 Q1 ic2= -8m vd 2 Figure 11.7 BJT differential amplifier with differential-mode input signal