A Darlington stage and a common-collectorcommon-emitter cascade are shown schematically in Fig. 7.40, where R S =

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A Darlington stage and a common-collector€“common-emitter cascade are shown schematically in Fig. 7.40, where RS= 100 kΩ and RL= 3 kΩ.

(a) Calculate the low-frequency small-signal voltage gain Ï…o/Ï…i for each circuit.

(b) Use the zero-value time-constant method to calculate the ˆ’3-dB frequency of the gain of each circuit. Data: β = 100, fT = 500 MHz at IC = 1 mA, Cμ = 0.4 pF,Cje = 2 pF, Ccs = 1 pF, rb = 0, r= ˆž, IC1 = 10 µA, and IC2 = 1mA. (Values of Cμ, Ccs, and Cje are at the bias point.)

Fig. 7.40:

Rg RL Vo Vị Q2 (a) Rs R1 Q2 Vo (b)

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Analysis and Design of Analog Integrated Circuits

ISBN: 978-0470245996

5th edition

Authors: Paul R. Gray, ‎ Paul J. Hurst Stephen H. Lewis, ‎ Robert G. Meyer

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