An integrated electronic subsystem is to be fabricated, which requires 40,000 square mils of silicon area. Determine whether the system should be put on one or two chips, assuming that the fabrication cost of the two chips is the only consideration. Assume that the wafer-fab cost is $100.00, the packaging and testing costs are $0.60, the die-fab yield is 0.9, and the final-test yield is 0.8. Assume the process used follows curve B in Fig. 2.68. Repeat the problem assuming yield curve A, and then yield curve C. Assume a 4-inch wafer.

Fig. 2.68.

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100 80 60 40 20 Process A 10 Process B Process C 10 20 30 40 50 60 70 80 90 100 Die size (mil? x 10) 4. 2. Yws (yield, %)