Design the circuit of Fig. 4.11b to satisfy the constraints in Problem 4.3 except the output resistance objective is that the output current change less than 0.02 percent for a 1 V change in the output voltage. Ignore the body effect for simplicity. Make all devices identical except for M₄. Use SPICE to check your design and also to plot the I_OUT-V_OUTcharacteristic for V_OUTfrom 0 to 3 V. λ

Figure 4.11b:

(a) MOS cascode current mirror with improved biasing for maximum voltage swing. (b) Practical implementation. (c) I-V characteristic.

Transcribed Image Text:

IOUT VDD 2V. (2V, + 3Ve) VOUT OUT (c) (V, + 2Vm) Ms T 4 L M2 VOUT м Me (V, + Vm) Mз L.