For the source follower in Fig. 7.13b, find the low-frequency gain and plot the magnitude and phase of its voltage gain versus frequency from f = 10 kHz to f = 20 GHz, using log scales. Compare your plot with a SPICE simulation. Use the transistor data given in Problem 7.2 with a resistive load of 1 kΩ and then a capacitive load of 400 pF. In both cases, take I_D= 0.5 mA. Use a 1-mV input pulse amplitude with zero rise time. Comment on the shape of the time-domain responses. (Bias the circuit with an ideal 0.5 mA current source connected to the source for the capacitive load test.)

Data from Prob. 7.2:

The following NMOS transistor data: NMOS: W = 100 µm, L_drwn = 2 µm, L_d = 0.2 µm, X_d = 0, λ = 0, k€™_n = 60 µA/V², γ = 0, C_sb = C_db = 0, C_ox = 0.7 fF/(µm²), and C_gd = 14 fF.

Fig. 7.13 b:

Transcribed Image Text:

Rs Vo R