The input stages of an op amp are shown in the schematic of Fig. 9.59.

(a) Assuming that the frequency response is dominated by a single pole, calculate the frequency where the magnitude of the small-signal voltage gain | Ï…_o (jω) /Ï…_i (jω) | is unity and also the output slew rate of the amplifier.

(b) Sketch the response V_o(t) from 0 to 20 µs for a step input at V_i from ˆ’5 V to +5 V. Assume that the circuit is connected in a non-inverting unity-gain feedback loop.

Compare your results with a SPICE simulation using parameters β = 100, V_A = 130 V, and I_S = 10^ˆ’15 A for all devices.

Fig. 9.59:

Transcribed Image Text:

+15 V 1ΕE () 20 μΑ 300 μΑ Οι Q2 10 pF V; Q5 Q4 50 kΩ Q3 -15 V