A description of a 74194 4-bit bidirectional shift register follows. 

The CLRb input is asynchronous and active low and overrides all the other control inputs. All other state changes occur following the rising edge of the clock. If the control inputs S₁ = S₀ = 1, the register is loaded in parallel. If S₁ = 1 and S₀ = 0, the register is shifted right and SDR (serial data right) is shifted into Q₃. If S₁ = 0 and S₀ = 1, the register is shifted left and SDL is shifted into Q₀. If S₁ = S₀ = 0, no action occurs.

(a) Write a behavioral-level Verilog model for the 74194.
(b) Draw a block diagram and write a Verilog description of an 8-bit bidirectional shift register that uses two 74194s as components. The parallel inputs and outputs to the 8-bit register should be X([7:0]) and Y([7:0]). The serial inputs should be RSD and LSD.

Transcribed Image Text:

Q3 Q2 SDR SDL S1 O- CLRB 74194 So CLK Do D1 D3 D2