For the given SM chart,

(a) Complete the following timing diagram (assume that X₁ = 1, X₂ = 0, X₃ = 0, X₅ = 1, and X₄ is as shown). Flip-flops change state on falling edge of clock.

(b) Using the given one-hot state assignment, derive the minimum next state and output equations by inspection of the SM chart.
(c) Write a Verilog description of the digital system.

Transcribed Image Text:

| 001 (Q3 Q2 Q1) Sol X1 (X2 Z, S,IZ3 | 100 010 X3 X4 X5 Z3 Clock X4 Q2 Q3