The objective of this problem is to use Verilog to describe and simulate a multiplier for signed
Question:
(A) So the sign bit will not be lost if an overflow occurs. Also, use an (n + 1)-bit register.
(B) To hold the multiplier and an n-bit register.
(C) To hold the multiplicand.
1. Clear A (the accumulator), load the multiplier into the upper n bits of B, clear B0, and load the multiplicand into C.
2. Test the lower two bits of B (B1B0). If B1B0 = 01, add C to A (C should be sign-extended to n + 1 bits and added to A using an (n + 1)-bit adder).
If B1B0 = 10, add the 2s complement of C to A. If B1B0 = 00 or 11, skip this step.
3. Shift A and B together right one place with sign extended.
4. Repeat steps 2 and 3, n - 1 more times.
5. The product will be in A and B, except ignore B0.
Example for n = 5: Multiply 29 by -13.
(a) Draw a block diagram of the system for n = 8. Use 9-bit registers for A and B, a 9-bit full adder, an 8-bit complementer, a 3-bit counter, and a control circuit. Use the counter to count the number of shifts.
(b) Draw a state graph for the control circuit. When the counter is in state 111, return to the start state at the time the last shift occurs (three states should be sufficient).
(c) Write behavioral Verilog code for the multiplier.
(d) Simulate your Verilog design using the following test cases (in each pair, the second number is the multiplier):
01100110 Ã 00110011
10100110 Ã 01100110
Step by Step Answer:
Digital Systems Design Using Verilog
ISBN: 978-1285051079
1st edition
Authors: Charles Roth, Lizy K. John, Byeong Kil Lee