Consider the CMOS latch shown below. Assume VDD = 1V, gate capacitance of 3fF for both...
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Consider the C²MOS latch shown below. Assume VDD = 1V, gate capacitance of 3fF for both NMOS and PMOS (3fF is all of gate contribution for a given device), junction capacitance of 2fF for both NMOS and PMOS (2fF is all of source/drain contribution for a given device), and R₁ = R₂ = 2km. Do not ignore the internal node capacitances, but assume source/drain sharing wherever appropriate. There is no external load on output. a. (7) Calculate the worst case D to delay of this latch. Assume that the CK input has stabilized well before the clock transition. b. (7) Calculate the worst case CK to delay of this latch. Assume that the D input has stabilized well before the clock transition. c. (8) What are the latch setup and hold times? D СК. CK VDD M4 7 M3 M₂ M₁ Consider the C²MOS latch shown below. Assume VDD = 1V, gate capacitance of 3fF for both NMOS and PMOS (3fF is all of gate contribution for a given device), junction capacitance of 2fF for both NMOS and PMOS (2fF is all of source/drain contribution for a given device), and R₁ = R₂ = 2km. Do not ignore the internal node capacitances, but assume source/drain sharing wherever appropriate. There is no external load on output. a. (7) Calculate the worst case D to delay of this latch. Assume that the CK input has stabilized well before the clock transition. b. (7) Calculate the worst case CK to delay of this latch. Assume that the D input has stabilized well before the clock transition. c. (8) What are the latch setup and hold times? D СК. CK VDD M4 7 M3 M₂ M₁
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Related Book For
Analysis and Design of Analog Integrated Circuits
ISBN: 978-0470245996
5th edition
Authors: Paul R. Gray, ? Paul J. Hurst Stephen H. Lewis, ? Robert G. Meyer
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