Consider the following sequence of instructions

ADD    #20, R0, R1

MUL    #3, R2, R3

AND    #$3A, R2, R4

ADD    R0, R2, R5

In all instructions, the destination operand is given last. Initially, registers R0 and R2 contain 2000 and 50, respectively. These instructions are executed in a computer that has a four-stage pipeline. Assume that the first instruction is fetched in clock cycle 1, and that instruction fetch requires only one clock cycle.

Draw a diagram describing the operation being performed by each pipeline stage during each of clock cycles 1 through 4.