In the circuit of Fig. 5.8, (W/L)N = 10/0.5, (W/L)p = 10/0.5, and IREF = 100...

  

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In the circuit of Fig. 5.8, (W/L)N = 10/0.5, (W/L)p = 10/0.5, and IREF = 100 µA. The input CM level applied to the gates of M, and M2 is equal to 1.3 V. (a) Assuming A = 0, calculate Vp and the drain voltage of the PMOS diode-connected transistors. Figure 5.8 Current mirrors used to bias a differential amplifier. VD M3 M4 M5 REF 0.4/T 0.4/T 北 M1 M2 Mo 卡 W. In the circuit of Fig. 5.8, (W/L)N = 10/0.5, (W/L)p = 10/0.5, and IREF = 100 µA. The input CM level applied to the gates of M, and M2 is equal to 1.3 V. (a) Assuming A = 0, calculate Vp and the drain voltage of the PMOS diode-connected transistors. Figure 5.8 Current mirrors used to bias a differential amplifier. VD M3 M4 M5 REF 0.4/T 0.4/T 北 M1 M2 Mo 卡 W.