Consider Figure 20.20. Assume that each gate produces a delay of 10 ns. Thus, the sum output

Question:

Consider Figure 20.20. Assume that each gate produces a delay of 10 ns. Thus, the sum output is valid after 30 ns and the carry output after 0 ns. What is the total add time for
a. 32-bit adder
a. Implemented without carry look ahead, as in Figure 20.19?
b. Implemented with carry look ahead and using 8-bit adders, as in Figure 20.21?