Consider the following problem. A designer has available a chip and decided what fraction of the chip will be devoted to cache memory (L1, L2, L3). The remainder of the chip can be devoted to a single complex superscalar and/or SMT core or multiple somewhat simpler cores. Define the following parameters:
n = maximum number of cores that can be contained on the chip
k = actual number of cores implemented (1 perf(r) = sequential performance gain by using the resources equivalent to r cores to form a single processor, where perf(1) = 1.
f = fraction of software that is parallelizable across multiple cores.
Thus, if we construct a chip with n cores, we expect each core to provide sequential performance of 1 and for the n cores to be able to exploit parallelism up to a degree of n parallel threads. Similarly, if the chip has k cores, then each core should exhibit a performance of perf(r) and the chip is able to exploit parallelism up to a degree of k parallel threads. We can modify Amdhal's law (Equation 18.1) to reflect this situation as follows:

a. Justify this modification of Amdahl's law.
b. Using Pollack's rule, we set perf(r) = ˆšr. Let n = 16. We want to plot speedup as a function of r for f = 0.5; f = 0.9; f = 0.975; f = 0.99. The results are available in a document at this book's Web site (multicore-performance.pdf). What conclusions can you draw?
c. Repeat part (b) for n = 256.

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Speedup f x r perf r) perf(r) X n