Design a CMOS op amp based on the folded-cascode architecture of Fig. 6.28 using supply voltages of ± 1.5 V. Use the bias circuit of Fig. 4.42 (with M₃and M₄cascoded) to generate the bias current I_BIAS. Then design an extension to this bias circuit that

produces the bias voltagesV_BIAS1, V_BIAS2, and V_BIAS3 based on I_BIAS. The output current-drive capability is to be ± 100 μA, the output voltage-swing capability 1.5 Volts peak-peak, and the input common-mode range should extend from 0.5 V to the negative supply. Matching requirements dictate a minimum effective channel length of 1μm. To make the gain insensitive to small shifts in the operating point, design the circuit so that the magnitude of the drain-source voltage for each transistor operating in the active region exceeds the magnitude of its overdrive by at least 100 mV. Specify all device geometries and bias currents. The process is then-well process with parameters given in Table 2.4. Assume X_d =0 and γ = 0.25V ^½ for both n- and p-channel transistors, but ignore the body effect in the hand calculations. Use SPICE to verify and refine your design as well as to determine the gain.

Figure 4.42

Table 2.4

Transcribed Image Text:

VDp = 1.5 V 150 150 150 M7 M5 M8 Vi M2 M1 150 150 200 μΑ 5 pF M6 100 Мз 50 50 -VDp = -1.5 V VDD M109 M103 M102, VBIAS1 M108 M104 M101 o VBIAS2 M105 o VBIAS3 IBIAS O M107, M106 -Vss