If we change load/store instructions to use a register (without an offset) as the address, these instructions no longer need to use the ALU.

(See Exercise 4.15.) As a result, the MEM and EX stages can be overlapped and the pipeline has only four stages.

1. How will the reduction in pipeline depth affect the cycle time?

2. How might this change improve the performance of the pipeline?

3. How might this change degrade the performance of the pipeline?

Data from Exercise 4.15

lw is the instruction with the longest latency on the CPU from Section 4.4. If we modified lw and sw so that there was no offset (i.e., the address to be loaded from/stored to must be calculated and placed in rs before calling lw/sw), then no instruction would use both the ALU and Data memory. This would allow us to reduce the clock cycle time.

However, it would also increase the number of instructions, because many ld and sd instructions would need to be replaced with lw/add or sw/add combinations.

1. What would the new clock cycle time be?

2. Would a program with the instruction mix presented in Exercise 4.7 run faster or slower on this new CPU? By how much? (For simplicity, assume every lw and sw instruction is replaced with a sequence of two instructions.)

3. What is the primary factor that influences whether a program will run faster or slower on the new CPU?

4. Do you consider the original CPU (as shown in Figure 4.21) a better overall design; or do you consider the new CPU a better overall design? Why?

Figure 4.21

Transcribed Image Text:

PC Add Read address Instruction (31-01 Instruction [31-26] Instruction [25-21] Instruction [20-16] Instruction Instruction [15-11] memory Control Instruction [15-0] RegDst Branch MemRead MemtoReg ALUOP MemWrite ALUSro RegWrite Read register 1 Read data 1 Read register 2 Write Read register data 2 Write data Registers 16 Sign- extend 32 Instruction [5-0] Shift left 2, MUX ALU Add, result ALU control Zero ALU result ALU o Max Read data Address Data Write data memory MX