Although the dynamic power is the primary source of power dissipation in CMOS, leakage current produces a static power dissipation V × I_leak. The smaller the on chip dimensions, the more significant is the static power. Assume the figures shown in the following table for static and dynamic power dissipation for several generations of processors.

If the total dissipated power is reduced by 10% while maintaining the static to total power rate of problem 1.9.1, how much should the voltage be reduced to maintain the same leakage current?

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a. b. Technology 180 nm 70 nm Dynamic Power (W) Static Power (W) 10 60 50 90 Voltage (V) 1.2 0.9