In older processors such as the Intel Pentium or Alpha 21264, the second level of cache was external (located on a different chip) from the main processor and the irst level cache. While this allowed for large second level caches, the latency to access the cache was much higher, and the bandwidth was typically lower because the second level cache ran at a lower frequency. Assume a 512 KB offchip second level cache has a global miss rate of 4%. If each additional 512 KB of cache lowered global miss rates by 0.7%, and the cache had a total access time of 50 cycles, how big would the cache have to be to match the performance of the second level direct-mapped cache listed in the table? Of the eight-way set associative cache?

Multilevel caching is an important technique to overcome the limited amount of space that a First level cache can provide while still maintaining its speed. Consider a processor with the following parameters:

Transcribed Image Text:

1.0 1.5 2 GHz 2 GHz 150 ns 100 ns 3% 7% 15 cycles 12 cycles 5.0% 3.5% 20 cycles 28 cycles 2.0% 1.5% Base CPI, No Memory Stalls Processor Speed Main Memory Access Time First Level Cache Miss Rate per Instruction Second Level Cache, Direct-Mapped Speed Global Miss Rate with Second Level Cache, Direct-Mapped Second Level Cache, Eight-Way Set Associative Speed Global Miss Rate with Second Level Cache, Eight-Way Set Associative