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computer science
systems analysis design
Questions and Answers of
Systems Analysis Design
Describe an IC bus at the following OSI-compliant levels of detail:a. physicalb. data linkc. networkd. transport
Determine how much logic in an FPGA must be devoted to a PCIe bus interface and how much would be left for an accelerator core.
You are designing an embedded system using an Intel Atom as a host. Does it make sense to add an accelerator to implement the function z = ax + by + c? Explain.
Develop a debugging scheme for an accelerator. Determine how you would easily enter data into the accelerator and easily observe its behavior. You will need to verify the system thoroughly, starting
You are designing an accelerated system that performs the following function as its main task:Assume that the accelerator has the entire pix and f arrays in its internal memory during the entire
You are designing an embedded system using an embedded processor with no floating-point support as host. Does it make sense to add an accelerator to implement the floating-point function S = A
Develop a generic streaming interface for an accelerator. The interface should allow streaming data to be read by the accelerator from the host’s memory. It should also allow streaming data to be
You are designing an embedded system using a high-performance embedded processor with floating point as host. Does it make sense to add an accelerator to implement the floating-point function S = A
Assume you want to use random tests on an FIR filter program. How would you know when the program under test is executing correctly?
Three devices are attached to a microprocessor: Device 1 has highest priority and device 3 has lowest priority. Each device’s interrupt handler takes 5 time units to execute. Show what interrupt
Provide examples of how each of the following can occur in a typical program:a. compulsory missb. capacity missc. conflict miss
Draw a UML sequence diagram for an interrupt-driven write of a device. The diagram should include the background program, the handler, and the device.
Draw a UML sequence diagram for a vectored interrupt-driven read of a device. The diagram should include the background program, the interrupt vector table, the handler, and the device.
Draw a UML sequence diagram for copying characters from an input to an output device using interrupt-driven I/O. The diagram should include the two devices and the two I/O handlers.
Draw a UML sequence diagram of a higher-priority interrupt that happens during a lower-priority interrupt handler. The diagram should include the device, the two handlers, and the background program.
Draw a UML sequence diagram of a lower-priority interrupt that happens during a higher-priority interrupt handler. The diagram should include the device, the two handlers, and the background program.
Draw a UML sequence diagram of a nonmaskable interrupt that happens during a low-priority interrupt handler. The diagram should include the device, the two handlers, and the background program.
Draw a UML state diagram for the steps performed by an ARM7 when it responds to an interrupt.
Draw a UML sequence diagram that shows how an ARM processor goes into supervisor mode. The diagram should include the supervisor mode program and the user mode program.
Give three examples of typical types of exceptions handled by CPUs.
What are traps used for?
Draw a UML sequence diagram that shows how an ARM processor handles a floating-point exception. The diagram should include the user program, the exception handler, and the exception handler table.
What is the average memory access time of a machine whose hit rate is 96%, with a cache access time of 3 ns and a main memory access time of 70 ns?
If we want an average memory access time of 6.5 ns, our cache access time is 5 ns, and our main memory access time is 80 ns, what cache hit rate must we achieve?
In the two-way, set-associative cache with four banks of Example 3.8, show the state of the cache after each memory access, as was done for the directmapped cache. Use an LRU replacement policy.
The following code is executed by an ARM processor with each instruction executed exactly once:Show the contents of the instruction cache for these configurations, assuming each line holds one ARM
Show a UML state diagram for a paged address translation using a flat page table.
Show a UML state diagram for a paged address translation using a three level, tree-structured page table.
What are the stages in an ARM 7 pipeline?
What are the stages in the C55x pipeline?
What is the difference between latency and throughput?
Draw a pipeline diagram for an ARM7 pipeline’s execution of three fictional instructions: aa, bb, and cc. The aa instruction always requires two cycles to complete the execute stage. The cc
Draw two pipeline diagrams showing what happens when an ARM BZ instruction is taken and not taken, respectively.
Name three mechanisms by which a CMOS microprocessor consumes power.
Provide a user-level example ofa. static power managementb. dynamic power management
Why cannot you use the same mechanism to return from a sleep power saving state as you do from an idle power-saving state?
Name three major components of a generic computing platform.
Use a logic analyzer to view system activity on your bus.
If your CPU has a pipeline that gives different execution times when a branch is taken or not taken, write a program in which these branches take different amounts of time. Use a CPU simulator to
Write ARM code that tests a register at location ds1 and continues execution only when the register is nonzero.
Measure the time required to respond to an interrupt.
Write ARM code that waits for the low-order bit of device register ds1 to become 1 and then reads a value from register dd1.
Implement peek() and poke() in assembly language for ARM.
Draw a UML sequence diagram for a busy-wait read of a device. The diagram should include the program running on the CPU and the device.
Draw a UML sequence diagram for a busy-wait write of a device. The diagram should include the program running on the CPU and the device.
Draw a UML sequence diagram for copying characters from an input to an output device using busy-wait I/O. The diagram should include the two devices and the two busy-wait I/O handlers.
What role does the HAL play in the platform?
If your logic analyzer is capable of on-the-fly disassembly, use it to display bus activity in the form of instructions, rather than simply 1s and 0s.
Draw UML state diagrams for device 1 and device 2 in a four-cycle handshake.
Attach LEDs to your system bus so that you can monitor its activity. For example, use an LED to monitor the read/write line on the bus.
Describe the role of these signals in a bus:a. R/W’b. data readyc. clock
Design logic to interface an I/O device to your microprocessor.
Draw a UML sequence diagram that shows a four-cycle handshake between a bus master and a device.
Use a data dump program to study the format of data on a flash memory card used as a file system.
Define these signal types in a timing diagram:a. changing;b. stable.
Have someone else deliberately introduce a bug into one of your programs, and then use the appropriate debugging tools to find and correct the bug.
Draw a timing diagram with the following signals (where [t1,t2] is the time interval starting at t1 and ending at t2):a. signal A is stable [0,10], changing [10,15], stable [15,30]b. signal B is 1
Identify the different bus transaction types in your platform. Compute the bestcase bus bandwidth.
Draw a timing diagram for a read operation on a bus in which the read includes two wait states.
Construct a simple program to perform some memory accesses. Use a logic analyzer to study the bus activity. Determine what types of bus modes are used for the transfers.
Construct a simple program to access memory in widely separated places.Measure the memory system bandwidth and compare to the best-case bandwidth.
Draw a timing diagram for a write operation on a bus in which the write takes two wait states.
Draw a timing diagram for a write operation with no wait states.
When would you prefer to use busy-wait I/O over interrupt-driven I/O?
Draw UML diagrams for the read of one character from an 8251 UART. To read the character from the UART, the device needs to read from the data register and to set the serial port status register bit
If you could only have one of vectors or priorities in your interrupt system, which would you rather have?
Draw a UML state diagram for software processing of a vectored interrupt.The vector handling is performed by software (a generic driver) that executes as the result of an interrupt. Assume that the
Draw a UML sequence diagram for an interrupt-driven read of a device.The diagram should include the background program, the handler, and the device.
Why do most programs use interrupt-driven I/O over busy/wait?
Why do most computer systems use memory-mapped I/O?
Write a simple loop that lets you exercise the cache. By changing the number of statements in the loop body, you can vary the cache hit rate of the loop as it executes. If your microprocessor fetches
Draw a timing diagram for a burst write operation that writes four locations.
Draw a UML state diagram for a burst read operation with wait states. One state diagram is for the bus master and the other is for the device being read.
Draw a UML sequence diagram for a burst read operation with wait states.
Draw timing diagrams fora. a device becoming bus masterb. the device returning control of the bus to the CPU
Draw a UML sequence diagram for a complete DMA transaction, including the DMA controller requesting the bus, the DMA transaction itself, and returning control of the bus to the CPU.
Draw a UML sequence diagram that shows a DMA bus transaction and concurrent processing on the CPU.
Draw a timing diagram that shows a complete DMA operation, including handing off the bus to the DMA controller, performing the DMA transfer, and returning bus control back to the CPU.
Draw UML state diagrams for a bus mastership transaction in which one side shows the CPU as the default bus master and the other shows the device that can request bus mastership.
Draw a UML sequence diagram for a bus mastership request, grant, and return.
Draw a UML sequence diagram showing a read operation across a bus bridge.
Draw a UML sequence diagram showing a write operation with wait states across a bus bridge.
Draw a UML sequence diagram for a read transaction that includes a DRAM refresh operation. The sequence diagram should include the CPU, the DRAM interface, and the DRAM internals to show the refresh
Draw a UML sequence diagram for an SDRAM read operation. Show the activity of each of the SDRAM signals.
What is the role of a memory controller in a computing platform?
What hardware factors might be considered when choosing a computing platform?
What software factors might be considered when choosing a computing platform?
Write ARM assembly language code that handles a breakpoint. It should save the necessary registers, call a subroutine to communicate with the host, and upon return from the host, cause the
Assume an A/D converter is supplying samples at 44.1 kHz.a. How much time is available per sample for CPU operations?b. If the interrupt handler executes 100 instructions obtaining the sample and
If an interrupt handler executes for too long and the next interrupt occurs before the last call to the handler has finished, what happens?
Consider a system in which an interrupt handler passes on samples to an FIR filter program that runs in the background.a. If the interrupt handler takes too long, how does the FIR filters output
Assume that your microprocessor implements an ICE instruction that asserts a bus signal that causes a microprocessor in-circuit emulator to start. Also assume that the microprocessor allows all
Why might an embedded computing system want to implement a DOScompatible file system?
Name two example embedded systems that implement a DOS-compatible file system.
You are given a memory system with an overhead O = 2 and a single-word transfer time of 1 (no wait states). You will use this memory system to perform a transfer of 1024 locations. Plot total number
You are given a bus which supports single-word and burst transfers. A single transfer takes 1 clock cycle (no wait states). The overhead of the single-word transfer is 1 clock cycles (O = 1). The
You are given a 2-byte wide bus that supports single-byte, dual-word (same clock cycle), and burst transfers of up to 8 bytes (4 byte pairs per burst). The overhead of each of these types of
Determine the design parameters for an audio system:a. Determine the total bytes per second required for an audio signal of 16 bits/sample per channel, two channels, sampled at 44.1 kHz.b. Given a
You are designing a system a bus-based computer: the input device I1 sends its data to program P1; P1 sends its output to output device O1. Is there any way to overlap bus transfers and computations
Compare the source code and assembly code for a moderate-size program.(Most C compilers will provide an assembly language listing with the -S flag.) Can you trace the high-level language statements
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