8.4-2. To satisfy the steady-state constraints for the system of Problem 8.2-3, the dc gain of the...

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8.4-2. To satisfy the steady-state constraints for the system of Problem 8.2-3, the dc gain of the digital controller must be equal 4

(a) Design a phase-lag controller with this dc gain that will result in a \(45^{\circ}\) phase margin.
(b) Estimate the percentage of overshoot in the step response of the compensated system.

(c) Verify the step-response results in part (b) using MATLAB. The step response will show an overshoot in the step response of approximately 24 percent.

Problem 8.2-3Consider the system of Problem 8.2-2. It is desired that the steady-state error constant for a unit-ramp

Problem 8.2-2Consider the system of Fig. P8.2-2 with T = 0.2. (a) Show that the pulse transfer function of the plant is

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Digital Control System Analysis And Design

ISBN: 9780132938310

4th Edition

Authors: Charles Phillips, H. Nagle, Aranya Chakrabortty

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