Each of the following VHDL modules contains an error. For brevity, only the architecture is shown; assume that the library use clause and entity declaration are correct. Explain the error and show how to fix it. 

(a) 

(b)

(c)

(d)

(e)

(f)

(g)

Transcribed Image Text:

architecture synth of latch is begin process(clk) begin if clk ='1' then q <= d; end if: end process: end: architecture proc of gates is begin process(a) begin Y1 <= a and b: y2 <= a or b; y3 <= a xor b: y4 <= a nand b: y5 <= a nor b: end process: end: