In VHDL, why is it necessary to write q < = '1' when state = S0 else

Question:

In VHDL, why is it necessary to write 

q < = '1' when state = S0 else '0' ;

rather than simply 

q < = (state =S0);

Fantastic news! We've Found the answer you've been seeking!

Step by Step Answer:

Related Book For  book-img-for-question
Question Posted: