(a) Figure 4-12 shows the block diagram for a 32-bit serial adder with accumulator. The control circuit uses a 5-bit counter, which outputs a signal K = 1 when it is in state 11111. When a start signal (St) is received, the registers should be loaded. Assume that St will remain 1 until the addition is complete. When the addition is complete, the control circuit should go to a stop state and remain there until St is changed back to 0. Draw a state diagram for the control circuit (excluding the counter).
(b) Write the Verilog for the complete system and verify its correct operation.