A sequential circuit has one input (X) and two outputs (Z 1 and Z 2 ). An

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A sequential circuit has one input (X) and two outputs (Z1 and Z2). An output Z1 = 1 occurs every time the input sequence 010 is completed provided that the sequence
100 has never occurred. An output Z2 = 1 occurs every time the input sequence 100 is completed. Once a Z2 = 1 output has occurred, Z1 = 1 can never occur, but not vice versa.
(a) Derive a Mealy state graph and table with a minimum number of states (eight states).
(b) Try to choose a good state assignment. Realize the circuit using J-K flip-flops and NAND gates. Repeat using NOR gates.

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Digital Systems Design Using Verilog

ISBN: 978-1285051079

1st edition

Authors: Charles Roth, Lizy K. John, Byeong Kil Lee

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