A synchronous sequential circuit has one input and one output. If the input sequence 0101 or 0110
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A synchronous sequential circuit has one input and one output. If the input sequence 0101 or 0110 occurs, an output of two successive 1s will occur. The first of these 1s should occur coincident with the last input of the 0101 or 0110 sequence. The circuit should reset when the second 1 output occurs. For example,
input sequence: X = 010011101010 101101 ...
output sequence: Z = 000000000011 000011 ...
(a) Derive a Mealy state graph and table with a minimum number of states (six states).
(b) Try to choose a good state assignment. Realize the circuit using J-K flip-flops and NAND gates. Repeat using NOR gates.
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a b Guidelines I 013045 II 0112341505 III 01234535 For state assignment S0 000 S1 ...View the full answer
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Related Book For 
Digital Systems Design Using Verilog
ISBN: 978-1285051079
1st edition
Authors: Charles Roth, Lizy K. John, Byeong Kil Lee
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