Modify the AHDL code in Figure 6-23 to create a 4-bit parallel adder. Figure 6-23 1 SUBDESIGN

Modify the AHDL code in Figure 6-23 to create a 4-bit parallel adder.

Figure 6-23

Transcribed Image Text:

1 SUBDESIGN fig6_23 495SWNT 2 ( 3 a [7..0] b[7..0] s [8..0] 6 ) 7 VARIABLE aa [8..0] bb [8..0] BEGIN aa [8..0] = bb [8..0] = s [8..0] END; 098 10 11 12 13 14 M = : INPUT; :INPUT; :OUTPUT; :NODE; :NODE; (GND, a [7..0]); (GND, b[7..0]); aa [8..0] + bb [8..0]; 8-bit augend 8-bit addend -- 9-bit sum -- -- -- -- -- -- expanded augend expanded addend concatenate leading zero to both operands -- add expanded operands