Refer to Figure 6-10. Assume that each FF has t_PLH = t_PHL = 30 ns and a setup time of 10 ns, and that each FA has a propagation delay of 40 ns. What is the minimum time allowed between the PGT of the LOAD pulse and the PGT of the TRANSFER pulse for proper operation?

Figure 6-10

Transcribed Image Text:

LOAD> C4 CLEAR> TRANSFER> CLKD FA D >CLK B₂ A₂ CLR CLEAR LOAD TRANSFER I I 4 1 T CLK D DCLK 12 FA CLR D B₂ A₂ T 1 13 S₁ CLK 1₂ FA D >CLK CLR (h) D B₂ 100 A₁ Accumulator outputs (a) 1 1 5 Sor CLK D FA D >CLK CLR Bo Ao B register -Co 4-bit adder A register