Refer to the counter circuit in Figure 5-48. Assume that all asynchronous inputs are connected to VCC.
Question:
Refer to the counter circuit in Figure 5-48. Assume that all asynchronous inputs are connected to VCC. When tested, the circuit waveforms appear as shown in Figure 5-101. Consider the following list of possible faults. For each one, indicate “yes” or “no” as to whether it could cause the observed results. Explain each response.
(a) CLR input of X2 is open.
(b) X1 output’s transition times are too long, possibly due to loading.
(c) X2 output is shorted to ground.
(d) X2’s hold time requirement is not being met
Figure 5-48
Figure 5-101
Transcribed Image Text:
Clock pulses Qo *All PRE and CLR are HIGH Q₁ J Q₂ Count Q₂Q₁Q0. CLK K 1 CLK போடா ITQ₁ 0 0 a 0 la I J O CLK TQ3 K (a) 10 1 1 (b) J 5 6 7 8 9 10 i CLK 1 K Qo 11 18 tuti Input clock pulses 1 1 T I 000001010 011 100 101 110 111 000 001010100 | I 1
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Related Book For
Digital Systems Principles And Application
ISBN: 9780134220130
12th Edition
Authors: Ronald Tocci, Neal Widmer, Gregory Moss
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