The 21256 is a 256K × 1 DRAM that consists of a 512 × 512 array of cells. The cells must be refreshed within 4 ms for data to be retained. Each time a C̅A̅S̅ before R̅A̅S̅ refresh cycle occurs, the on-chip refresh circuitry will refresh a row of the array at the row address specified by a refresh counter. The counter is incremented after each refresh. How often should C̅A̅S̅-before- R̅A̅S̅ cycles be applied in order for all of the data to be retained?